Cypress Semiconductor /psoc63 /I2S0 /INTR_MASKED

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTR_MASKED

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_TRIGGER)TX_TRIGGER 0 (TX_NOT_FULL)TX_NOT_FULL 0 (TX_EMPTY)TX_EMPTY 0 (TX_OVERFLOW)TX_OVERFLOW 0 (TX_UNDERFLOW)TX_UNDERFLOW 0 (TX_WD)TX_WD 0 (RX_TRIGGER)RX_TRIGGER 0 (RX_NOT_EMPTY)RX_NOT_EMPTY 0 (RX_FULL)RX_FULL 0 (RX_OVERFLOW)RX_OVERFLOW 0 (RX_UNDERFLOW)RX_UNDERFLOW 0 (RX_WD)RX_WD

Description

Interrupt masked register

Fields

TX_TRIGGER

Logical and of corresponding request and mask bits.

TX_NOT_FULL

Logical and of corresponding request and mask bits.

TX_EMPTY

Logical and of corresponding request and mask bits.

TX_OVERFLOW

Logical and of corresponding request and mask bits.

TX_UNDERFLOW

Logical and of corresponding request and mask bits.

TX_WD

Logical and of corresponding request and mask bits.

RX_TRIGGER

Logical and of corresponding request and mask bits.

RX_NOT_EMPTY

Logical and of corresponding request and mask bits.

RX_FULL

Logical and of corresponding request and mask bits.

RX_OVERFLOW

Logical and of corresponding request and mask bits.

RX_UNDERFLOW

Logical and of corresponding request and mask bits.

RX_WD

Logical and of corresponding request and mask bits.

Links

() ()